Pinned Loading
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eecs151_FPGA_RISC-V_Project
eecs151_FPGA_RISC-V_Project PublicTarget tech: Xilinx Zynq-7020 (Digilent PYNQ Z1 dev board)
Verilog 2
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UC_Berkeley_251a_ASIC_RV32I_project
UC_Berkeley_251a_ASIC_RV32I_project PublicThis little ASIC design was taken through the (almost) full RTL-GDS flow using commercial EDA tools (VCS, Cadence Genus, Innovus, Siemens Calibre) with sky130 node
Verilog 2
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RTL_DV_UVM_experiments
RTL_DV_UVM_experiments PublicExploration of the best SystemVerilog (IEEE 1800-2023) practices and more
SystemVerilog
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opencloud_devops
opencloud_devops PublicSelf-hosted OpenCloud with Prometheus and Grafana monitoring
HCL
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nvim-config
nvim-config PublicCustom, lean, but quite powerful nvim config. Quite heavy on custom keybindings.
Lua
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